Verification of Transaction Level Models of Embedded Systems
As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, w...
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| Formato: | Online |
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Universidad de Costa Rica
2013
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| Acceso en línea: | https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662 |
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INGE11662 |
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INGE116622020-08-11T16:04:57Z Verification of Transaction Level Models of Embedded Systems Yu Lo, Lucky Lochi Embedded Systems Verification Embedded Systems As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, we propose a methodology to do formal verification of embedded systems. In formal verification no test cases are needed, but an mathematical analysis of the original model and the refined one. We base our tool on the Model Algebra theory of embedded systems, and apply its transformation rules to our models to check for equivalency. We test this transformation rules in various scenarios and prove that it is a promising methodology to improve embedded system design. Universidad de Costa Rica 2013-11-19 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Article Artículo application/pdf text/html application/pdf https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662 10.15517/ring.v23i2.11662 Ingeniería; Vol. 23 No. 2 (2013): July-December 2013; 75-95 Ingeniería; Vol. 23 Núm. 2 (2013): Julio-Diciembre 2013; 75-95 Ingeniería; Vol. 23 N.º 2 (2013): Julio-Diciembre 2013; 75-95 2215-2652 1409-2441 spa https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662/pdf_19 https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662/html_23 https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662/34762 Derechos de autor 2014 Revista Ingeniería |
| institution |
Universidad de Costa Rica |
| collection |
Ingeniería |
| language |
spa |
| format |
Online |
| author |
Yu Lo, Lucky Lochi |
| spellingShingle |
Yu Lo, Lucky Lochi Verification of Transaction Level Models of Embedded Systems |
| author_facet |
Yu Lo, Lucky Lochi |
| author_sort |
Yu Lo, Lucky Lochi |
| description |
As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, we propose a methodology to do formal verification of embedded systems. In formal verification no test cases are needed, but an mathematical analysis of the original model and the refined one. We base our tool on the Model Algebra theory of embedded systems, and apply its transformation rules to our models to check for equivalency. We test this transformation rules in various scenarios and prove that it is a promising methodology to improve embedded system design. |
| title |
Verification of Transaction Level Models of Embedded Systems |
| title_short |
Verification of Transaction Level Models of Embedded Systems |
| title_full |
Verification of Transaction Level Models of Embedded Systems |
| title_fullStr |
Verification of Transaction Level Models of Embedded Systems |
| title_full_unstemmed |
Verification of Transaction Level Models of Embedded Systems |
| title_sort |
verification of transaction level models of embedded systems |
| publisher |
Universidad de Costa Rica |
| publishDate |
2013 |
| url |
https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662 |
| work_keys_str_mv |
AT yuloluckylochi verificationoftransactionlevelmodelsofembeddedsystems |
| _version_ |
1810112523934892032 |